1. Field of the Invention
The present invention relates to the field of signal drivers. More specifically, the present invention relates to the field of signal drivers within a programmable integrated circuit.
2. Background Technology
Programmable integrated circuits (ICs), such as field programmable gate arrays (FPGAs) utilize a number of drivers circuits ("buffers") to transmit signals internally and externally. Since the FPGAs contain a number of configurable logic circuits, the FPGAs also contain configurable or programmable interconnect structures ("interconnect structure") which allow a great degree of flexibility in coupling together the input and output signals of the configurable logic circuits. The interconnect structure, as is well known in the art, comprises a number of signal lines disposed between configurable logic circuits. The interconnect structure also contains a number of programmable interconnect points (PIPs) located at the intersection of signal lines. Each PIP comprises a pass transistor coupling the two intersecting signal lines. The pass transistor is controlled by a memory unit (e.g., antifuse or SRAM, etc.) whose programmed state determines whether or not the two intersecting lines are electrically coupled. PIPs of the kind described above are also well known in the art.
Since the interconnect structure is programmable, any given signal line within the interconnect structure can be driven by a number of different configurable logic circuits. Therefore, any given signal line of the interconnect structure can be driven in either direction depending on the particular configuration programmed into the interconnect structure. This particular characteristic of the signal lines can be problematic for signal buffering because signal buffering is typically performed using directional elements.
As a result, programmable interconnect structures of the past utilize configurable bi-directional buffers that allow a particular signal to be buffered in either direction along a signal line. Each configurable bi-directional buffer is programmable in that the particular direction for buffering is programmed into the bi-directional buffer during FPGA initialization (e.g., when the program information is loaded into the FPGA to configure the FPGA for operation).
A number of different bi-directional buffers are known in the art, see Hsieh U.S. Pat. No. 4,835,418 (May 30, 1989), entitled "Three State Bi-Directional Buffer," and Carter U.S. Pat. No. 4,695,740 (Sep. 22, 1987) entitled "BiDirectional Buffer Amplifier," and Carter U.S. Pat. No. 4,713,557 (Dec. 15, 1987) entitled "Bi-Directional Buffer Amplifier."
FIG. 1 illustrates one prior art bi-directional buffer circuit 10. This circuit 10 contains two input/output lines 20 and 22 and contains two programmable memory cells 12 and 14. The input/output lines 20 and 22 are part of the interconnect structure. The circuit 10 also contains two inverter circuits 16 and 18 to provide signal buffering. When memory cell 12 is "1" and memory cell 14 is "0," n-type transistors 30a and 32b are ON, and transistors 30b and 32a are OFF. This configuration allows an input signal over line 20 to be buffered and output over line 22. When memory cell 12 is "0" and memory cell 14 is "1," n-type transistors 30b and 32a are ON, and transistors 30a and 32b are OFF. This configuration allows an input signal over line 22 to be buffered and output over line 20. When both memory cells are programmed "0," the circuit 10 is an open circuit across lines 20 and 22.
In the past, these bi-directional buffers have been used to buffer long lines within the programmable interconnect structure. In many applications, an auxiliary or secondary line is to be buffered within the interconnect structure. More specifically, it is often desired to buffer the auxiliary line into the long lines of the interconnect structure. Although satisfactory in many applications, the above referenced bi-directional buffers are not entirely satisfactory for providing signal buffering for these auxiliary signal lines because the bi-directional buffers have only two input/output lines.
Accordingly, it is desirable to implement a buffer circuit that can readily allow bi-directional buffering between a first and a second input/output line but can also provide buffering for an auxiliary signal line. The present invention provides a circuit with such advantageous functionality. Secondly, it would be advantageous to provide such a buffer circuit using only a minimal number of signal driving circuits in order to maintain small the overall substrate area required to implement the buffer circuit. The present invention provides a buffer circuit with this advantageous characteristic.